module dataInMuxer16 (
    input wire clk,
    input wire rst,
    input wire write_en_1,
    input wire write_en_2,
    input wire write_en_3,
    input wire write_en_4,
    input wire write_en_5,
    input wire write_en_6,
    input wire write_en_7,
    input wire write_en_8,
    input wire write_en_9,
    input wire write_en_10,
    input wire write_en_11,
    input wire write_en_12,
    input wire write_en_13,
    input wire write_en_14,
    input wire write_en_15,
    input wire write_en_16,
    input wire [5:0] write_priority_in_1,
    input wire [5:0] write_priority_in_2,
    input wire [5:0] write_priority_in_3,
    input wire [5:0] write_priority_in_4,
    input wire [5:0] write_priority_in_5,
    input wire [5:0] write_priority_in_6,
    input wire [5:0] write_priority_in_7,
    input wire [5:0] write_priority_in_8,
    input wire [5:0] write_priority_in_9,
    input wire [5:0] write_priority_in_10,
    input wire [5:0] write_priority_in_11,
    input wire [5:0] write_priority_in_12,
    input wire [5:0] write_priority_in_13,
    input wire [5:0] write_priority_in_14,
    input wire [5:0] write_priority_in_15,
    input wire [5:0] write_priority_in_16,
    output reg [15:0] write_arbitration
);
    wire [3:0] arbitration_final;
    wire write_en_final;
    wire [5:0] part_priority_final;
    wire [3:0] part_arbitration [0:3];
    wire [3:0] part_write_en;
    wire [5:0] part_priority [0:3];

    always @(posedge clk) begin
        if (rst) begin
            write_arbitration <= 16'h0000;
        end
        else begin
            if (arbitration_final == 4'b0001) begin
                write_arbitration <= {12'b000000000000, part_arbitration[0]};
            end

            if (arbitration_final == 4'b0010) begin
                write_arbitration <= {8'b00000000, part_arbitration[1], 4'b0000};
            end

            if (arbitration_final == 4'b0100) begin
                write_arbitration <= {4'b0000, part_arbitration[2], 8'b00000000};
            end

            if (arbitration_final == 4'b1000) begin
                write_arbitration <= {part_arbitration[3], 12'b000000000000};
            end

            if (arbitration_final == 4'b0000) begin
                write_arbitration <= 16'h0000;
            end
        end
    end

    //第一层仲裁器
    priorityMuxer4 mux1(.clk(clk), .rst(rst), 
                        .write_en_1(write_en_1), .priority_1(write_priority_in_1), .write_en_2(write_en_2), .priority_2(write_priority_in_2), .write_en_3(write_en_3), .priority_3(write_priority_in_3), .write_en_4(write_en_4), .priority_4(write_priority_in_4), 
                        .priority_arbitration(part_arbitration[0]), .write_en_out(part_write_en[0]), .priority_out(part_priority[0]));

    priorityMuxer4 mux2(.clk(clk), .rst(rst), 
                        .write_en_1(write_en_5), .priority_1(write_priority_in_5), .write_en_2(write_en_6), .priority_2(write_priority_in_6), .write_en_3(write_en_7), .priority_3(write_priority_in_7), .write_en_4(write_en_8), .priority_4(write_priority_in_8), 
                        .priority_arbitration(part_arbitration[1]), .write_en_out(part_write_en[1]), .priority_out(part_priority[1]));

    priorityMuxer4 mux3(.clk(clk), .rst(rst), 
                        .write_en_1(write_en_9), .priority_1(write_priority_in_9), .write_en_2(write_en_10), .priority_2(write_priority_in_10), .write_en_3(write_en_11), .priority_3(write_priority_in_11), .write_en_4(write_en_12), .priority_4(write_priority_in_12), 
                        .priority_arbitration(part_arbitration[2]), .write_en_out(part_write_en[2]), .priority_out(part_priority[2]));

    priorityMuxer4 mux4(.clk(clk), .rst(rst), 
                        .write_en_1(write_en_13), .priority_1(write_priority_in_13), .write_en_2(write_en_14), .priority_2(write_priority_in_14), .write_en_3(write_en_15), .priority_3(write_priority_in_15), .write_en_4(write_en_16), .priority_4(write_priority_in_16), 
                        .priority_arbitration(part_arbitration[3]), .write_en_out(part_write_en[3]), .priority_out(part_priority[3]));

    //第二层仲裁器
    priorityMuxer4 mux5(.clk(clk), .rst(rst), 
                        .write_en_1(part_write_en[0]), .priority_1(part_priority[0]), .write_en_2(part_write_en[1]), .priority_2(part_priority[1]), .write_en_3(part_write_en[2]), .priority_3(part_priority[2]), .write_en_4(part_write_en[3]), .priority_4(part_priority[3]), 
                        .priority_arbitration(arbitration_final), .write_en_out(write_en_final), .priority_out(part_priority_final));
endmodule